Semiconductor memories conventionally receive memory commands from a memory controller. The memory commands may be a combination of signals, such as a chip select (CS), a write enable (WE), a column address strobe (CAS), and a row address strobe (RAS), to name a few. The combination of command signals may be received by a command decoder, which may generate internal commands based thereon. The command decoder, depending on the command type, read or write for example, may provide the corresponding internal signals to different or varied circuits internal to the memory so the commands are performed as required. Because the memories perform different commands, duplicate circuitry may be used to distinguish between command types within the memories. The duplicate circuitry may partially be required because the internal command signals may be similar. A path on which the commands propagate in the memories may be used to distinguish between command types. However, segments of the paths may be redundant and only included to distinguish the command types.
For example, memories have conventionally included separate command shifters for each command type. One command shifter may be used for reads and a separate command shifter may be used for writes. Including multiple command shifters, however, may consume large areas of semiconductor die and increase power consumption. The command shifters may further consume die area and power when their size is increased to accommodate longer expected latencies, for example. Command shifters may be included in a memory to provide desired operational latencies, such as CAS latency, CAS write latency, CAS additive latency, etc., necessary for proper operation of the memory. The separate command shifters for each command type, such as additive latency shifters and master-slave CAS write latency shifters, were needed because there could be an overlap in read and write commands and further because the physical signals used to represent the commands may be similar. As such, to ensure the commands were interpreted correctly, the separate shifters were used to assist in distinguishing command type. This redundant use of die area and power consumption may then unnecessarily impose size and power consumption penalties on memories. Therefore, there is a desire to reduce the number of shifters included in memory in order to reduce die size and power consumption.